Why setup? Why hold?

Who says chatting is bad habit! Here is a chat session between two friends about deadly dangerous setup and hold!! Don’t think that the person who is asking these questions doesn’t know about setup and hold. The term “setup” and “hold” is such a word in this VLSI – ASIC design world which only creates questions and questions and questions!

All readers can join hands in this chat! Comment forms are always online!!

BGG: I have a doubt after long time. Why is set up and hold in flip-flop?

KMM: I am honored!

BGG: Can you go beneath transistor and tell me. I know metastability state or charging or discharging of capacitor etc etc?

KMM: Then what you know?

BGG: But flip flop is combination of 2 latches

KMM: Tell whatever you know...may be it has answer!

BGG: And latch is level triggered.

BGG: If so whatever data will be sent two latches will be launched. Why metastability? Why set up time? Why data should be stable before clock edge? WHY SETUP? WHY HOLD?

KMM: So how two level triggered latches form an edge triggered flop??????? If you find answer for this you will get answer for your question!!

KMM: Below link can help u:

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

BGG: Didn’t get.....

See they are telling the same.... we can’t avoid metastability state so we have to make data stable before setup and hold....

BGG: But my question is why metastable state?

KMM: Go inside latch.... how it works???? Say one input is given...then when the output gets stabilized????? ??????Immediately ......or does it take some time....

Remember working of simple SR latch....

KMM: Just think...think and think....that will solve your problem

BGG: Any clue

KMM: You know that any latch output doesn’t stabilize immediately.....

Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1)...

So in this way it takes 2-3 data cycles....right....

This happens for both latches of flop...ok

Now you know that both latches won’t work together ...because you have arranged flop circuit such away that slave follows master

Means....when master latches the data slave sleeps

And then slave follows master....

Means slave releases the data which is latched earlier....

To latch the data, master takes 2-3 cycle

(As I explained earlier) same is the story for slave....

Now extend your imagination...

To a flop which is exclusively designed as edge triggered with basic gates itself

May be NOR or NAND...or may be based on CMOS full custom...

Same story applies here as well.....

All that happens is those 2-3 cycles to stabilize data....

Now imagine one data is under latching process...

May be one cycle is completed...

Data is not at stabilized within this latch...

Now if you allow one more input to enter what will happen to that data which was under process?????????

Naturally latch may start processing new input data or may go to unknown loop state that we call as metastable state...

Same applies for data that was already latched but about to leave out of the latch...

KMM: These two timing delay requirements ultimately constitute setup and hold

KMM: hold for time required for data to come out

While setup for data to get latched....

Hence hold is always related with launch clock

While setup is related with capture clock....

BGG: I am confused now

What hold when you have data already in flip flop? Then why launch edge?

KMM: Always remember that flop has latch structure.....means to say....

When one latch works another doesn't do any work....

BGG: So...

KMM: So if you take register to register connection....

When one is launching data next one is ready to receive data

BGG: yes

KMM: That’s all.....

It continues like that way.....

KMM: When first one is receiving next flop is ready to launch...and so on....

To summarize........it takes one clock cycle to complete the launch or capture....

That’s why we always say....present data ...previous data...and so on...

BGG: So what I understood was right we don’t need a reference for hold since it’s already in flop

KMM: That’s why for hold analysis no clock is considered or..."hold is not dependant on clock"

BGG: Even hold has to be checked for 2nd flop only...right? It’s not for 1st flop

KMM: Let me think ...how I can explain u...

BGG: shall I tell you what I understood if you don’t mind

Please

KMM: wait....

It’s true that hold value is taken from second flop

But remember every capture flop becomes launch flop for new data to be launched...

KMM: So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop

KMM: And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check

Or in other words....

Setup check for present data which is traveling...

Hold for new (future) data

Present data should reach the capture flop input before capture clock reaches there.....

(Setup check)

KMM: new data shouldn't reach too fast to capture flop so that present data doesn't corrupt

BGG: Ok let me analyze... will get back to you... thank you

Some Doubts !

Recently i had a good chat session with my new friend bgs and i feel it is good idea to share the same..... it may clear or evoke some more doubts you have in your mind. I have given chat session as it is to maintain the originality. Please bear with chatting short cuts and spelling errors !!

so here we go.......


bgs: hi
1st time online?
me: hi...
bgs: i have seen u 1st time online?
me: with u first time
bgs: hm
me: then whts up
bgs: where ru?
me: i was off from bangalore last one month
went to xyz
now ofcourse back in bangalore
bgs: so ur working in PD ri8?
me: ya.....
bgs: which tool
me: astro
bgs: ur working on project now?
me: at present no work....... enjoying free time.....
bgs: oh good
me: trying to learn something new
bgs: so ur online ri8
so what ur learning?
me: thats right !!
how to calculate gate delay?!!!!!!
bgs: shall i ask one doubt in DC
me: and UPF
ya..... come on
shoot me ... let me try
bgs: whats diff bet set_max_capacitance and set_load?
i dont know ans
me: set_max_capacitance applies on pin not on pin and net
but set_load applies capacitance constraint on both net and pin
i.e whole output port gets loaded
bgs: max cap of cell (pin) will be precalculated by lib vender whats the use of setting it again
for higher value
me: pin cap can vary based on fanout...using which u can control fanout
bgs: what?
me: ultimately u r trying to control fanout==>drive strength==>delay
load cap==Cpin+Cnet
either u try to model Cpin or Cnet or both together
as u know gate delay=function of (input transition, Cload)
where Cload=Cpin+Cnet
hence we have set_max_cap and set_load
bgs: 1 sec ....for example if i have and (a,b,y) im seting max cap for y as 2. but default value of y in lib is 1 will it violate
*andgate(a,b,y)
sud i keep set_max _cap on y
me: yes....then tool tries to find a cell that meets your constraint
bgs: oh yes its doing
thanku
one more thing doubt pls
one more doubt pls
me: no need to keep set_max_cap for each and every cell...its impossible...
try to provide a moderate value so that tool take care of high fanout net synthesis
bgs: what is diff between timing engine and timing engine PT
me: DC target is to synthesize the code efficiently.....PT works exclusively on timing analysis
DC-uses less accurate timing algorithm
PT -uses Arnoldi algorithm which is synopsys patented and considered to be very accurate
PT timing correllation with SPICE results are really great
DC-no netlist editing facility
PT can do netlist editing
PT can do crosstalk analysis DC cant
PT can do variation analysis DC cant
bgs: get_allternate_cell is available in DC
me: ya.... u can try to find altrenative cells
thats all
but ofcourse DC can do incremental compilation
bgs: in DC flow if timing is not met will they change constraints or its fixed
me: more important is with PT there are several designs successfully taped out !!!!!
u have two options... improve ur HDL code....if still doesnt work..u have to change constraints itself ..but this is last option
bgs: if constaints r not realistic?
me: what u mean by realistic?
bgs: for example u have clock period is 3 inputdelay is 2
me: input and out delays are always exceptional cases and those can controlled depending on external interfaces...
bgs: ya ur ri8
me: bgs..... let me take a cup of coffeeee
bgs: but timinig is not met
me: i will come back later
bgs: k carry on

18 minutes

me: u can shoot again.....but timinig is not met.....wht is the question

19 minutes

me: gayab???
bgs: ya im back
my question was do i have n option of changing constraints if its not met
as synthesis engineer what all constraints i can change
?
me: welll.... frankly speaking we cant change constraints at logic synthesis stage (physical synthesis onwards we have a little control on constraints !!)
with the available clock if u cant meet timing even after improvement in code, logic and data path optimizations in DC then the left option is to increase clock period itself !
bgs: do u mean to say clk source, n/w latency, uncertainity will given as spec
me: as a part of spec u wont get latency etc....u will get only clock frequency...thats what u have to cahnge finally
bgs: ya then can i play with uncertainity , input n output dely?
max n min delay
me: to certain extent.... provided that if u have back annotated info of similar designs implemented in previous designs....
but at first itself u have modeled everything based on previous design experiences...
then u cant relax those constraints further
bgs: what about drc constraints? can i change them
me: u can provided if u dont have problem with timing and power and reliability !
bgs: k
me: becuase ur timing may be ok but there may be drc violations...in that case power consumption can be more
bgs: so if can i change constraints(not clk period
) n met timing
me: and also imagine a person can carry 50kg... then he can go for 5 kms... now imagine same person is forced to carry 100 kg...can he walk 5kms (reliability issue)?
bgs: hm
me: if u have modeled ur constraints properly then there is no room to change it...
but if u have over constrained the design at first then u got violation...in that case u can relax constraints
bgs: k
so in DC we play with constaints n fix them
me: no..we play with data path optimizations and logic optimizations to achieve timing...
we play with low vt cells and high vt cells to meet timing and power
bgs: hey that we do in
PT
me: but remember...PT is mainly used for analysis
PT wont do any optimization by itself
bgs: k, in dc we make sure violation is clear then y PT?
me: as i said PT timing engine is more robust.... more accurate compared to DC..hence get clearance from PT as well
bgs: ok
one more doubt yar in pt im geting some violation what all option i have other than swap cell to clear violation
me: size the cell
before sizing try to see bottleneck cost
see the depth of data path...if it is large then probably it is better to send the netlist back to synthesis stage
for data path optimizations
bgs: size the cell is increasing drive strength only na
r some thing else?
me: u can increase or decrease...depending on the delay offered by the cell...
also u can add buffers just before a cell which is causing larger delay..
also recalculate path delay with true path analysis...
this u can get with path inspector
bgs: how to add buffer i have not tryed that option
what does recalculate path delay with true path analysis... do?
me: get_recalculated_timing_paths -from xyz -to abc
insert_buffer/remove_buffer
bgs: what does this do buy recalculating timing path?
me: u have to provide buffer name and cell name
bgs: by*
when will we use get_recalculated_timing_paths -from xyz -to abc
me: if u have small violations and less number of violations then use recalcu***
bgs: k
thanku so much
:)
me: what happens in general is while calculating delays worst delay corresponding to different timing arc is considered
hence timing analysis becomes pessimistic....
to make it more accurate tell the tool to calculate timing based on actual true timing arcs
when u do this u may not get any violation...in that case u can tape out !!!!!
hey bgs ....i am leaving now.... see u tomorrow for any more questions.....
hope u r happy now with so many cleared doubts..
bgs: hey thanks yar u gave ur valuable time!!!
ya im :-
)
:-)
me: have a great eve!