Who says chatting is bad habit! Here is a chat session between two friends about deadly dangerous setup and hold!! Don’t think that the person who is asking these questions doesn’t know about setup and hold. The term “setup” and “hold” is such a word in this VLSI – ASIC design world which only creates questions and questions and questions!
All readers can join hands in this chat! Comment forms are always online!!
BGG: I have a doubt after long time. Why is set up and hold in flip-flop?
KMM: I am honored!
BGG: Can you go beneath transistor and tell me. I know metastability state or charging or discharging of capacitor etc etc?
KMM: Then what you know?
BGG: But flip flop is combination of 2 latches
KMM: Tell whatever you know...may be it has answer!
BGG: And latch is level triggered.
BGG: If so whatever data will be sent two latches will be launched. Why metastability? Why set up time? Why data should be stable before clock edge? WHY SETUP? WHY HOLD?
KMM: So how two level triggered latches form an edge triggered flop??????? If you find answer for this you will get answer for your question!!
KMM: Below link can help u:
http://en.wikipedia.org/wiki/Flip-flop_(electronics)
BGG: Didn’t get.....
See they are telling the same.... we can’t avoid metastability state so we have to make data stable before setup and hold....
BGG: But my question is why metastable state?
KMM: Go inside latch.... how it works???? Say one input is given...then when the output gets stabilized????? ??????Immediately ......or does it take some time....
Remember working of simple SR latch....
KMM: Just think...think and think....that will solve your problem
BGG: Any clue
KMM: You know that any latch output doesn’t stabilize immediately.....
Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1)...
So in this way it takes 2-3 data cycles....right....
This happens for both latches of flop...ok
Now you know that both latches won’t work together ...because you have arranged flop circuit such away that slave follows master
Means....when master latches the data slave sleeps
And then slave follows master....
Means slave releases the data which is latched earlier....
To latch the data, master takes 2-3 cycle
(As I explained earlier) same is the story for slave....
Now extend your imagination...
To a flop which is exclusively designed as edge triggered with basic gates itself
May be NOR or NAND...or may be based on CMOS full custom...
Same story applies here as well.....
All that happens is those 2-3 cycles to stabilize data....
Now imagine one data is under latching process...
May be one cycle is completed...
Data is not at stabilized within this latch...
Now if you allow one more input to enter what will happen to that data which was under process?????????
Naturally latch may start processing new input data or may go to unknown loop state that we call as metastable state...
Same applies for data that was already latched but about to leave out of the latch...
KMM: These two timing delay requirements ultimately constitute setup and hold
KMM: hold for time required for data to come out
While setup for data to get latched....
Hence hold is always related with launch clock
While setup is related with capture clock....
BGG: I am confused now
What hold when you have data already in flip flop? Then why launch edge?
KMM: Always remember that flop has latch structure.....means to say....
When one latch works another doesn't do any work....
BGG: So...
KMM: So if you take register to register connection....
When one is launching data next one is ready to receive data
BGG: yes
KMM: That’s all.....
It continues like that way.....
KMM: When first one is receiving next flop is ready to launch...and so on....
To summarize........it takes one clock cycle to complete the launch or capture....
That’s why we always say....present data ...previous data...and so on...
BGG: So what I understood was right we don’t need a reference for hold since it’s already in flop
KMM: That’s why for hold analysis no clock is considered or..."hold is not dependant on clock"
BGG: Even hold has to be checked for 2nd flop only...right? It’s not for 1st flop
KMM: Let me think ...how I can explain u...
BGG: shall I tell you what I understood if you don’t mind
Please
KMM: wait....
It’s true that hold value is taken from second flop
But remember every capture flop becomes launch flop for new data to be launched...
KMM: So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop
KMM: And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check
Or in other words....
Setup check for present data which is traveling...
Hold for new (future) data
Present data should reach the capture flop input before capture clock reaches there.....
(Setup check)
KMM: new data shouldn't reach too fast to capture flop so that present data doesn't corrupt
BGG: Ok let me analyze... will get back to you... thank you
1 comments:
i have an analogy for this
imagine Person A is talking to Person B. and person C jumps in and start talking to person B spontaneously. Imagine the plight of person B. there is a probability that Person B may or may not completely comprehend/understand what Person C is saying or Person A is saying.
so Person B is in metastable state.
he should either say person C/A to stop talking and allow A/C to talk at a time.
this stopping allows person B to be in stable state
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